1. Field of the Invention
This invention relates to processors and, more particularly, to implementation of I/O expansion buses in computing systems.
2. Description of the Related Art
A particular feature of some computing systems is the ability to expand the system to add new features or to upgrade existing capabilities. Some computing systems may include an I/O expansion bus to allow for adding hardware into a computing system. Many of these systems will use an industry standard bus format such that standardized hardware may be used for expansion. Some examples of industry standard bus formats are Peripheral Component Interconnect (PCI®), Peripheral Component Interconnect Express (PCI Express® or PCIe®), Universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA).
Many peripherals may need to exchange data with a system memory or one or more processors. A Direct Memory Access (DMA) controller may be used to facilitate such data exchanges. A DMA controller may read data from a source and write the data to a destination without involvement from another processor in the systems, allowing the processors to engage in other tasks or idle in low power modes.
To improve execution performance, processors may include one or more levels of cache memories (commonly referred to as “caches”). A cache may be used to store frequently accessed instructions and/or memory data, and improve performance by reducing the time for the processor to retrieve these instructions and data. A processor may include a fast first-level (L1) cache backed by a larger, slower second-level (L2) cache. Some processors may include a third-level (L3) cache for further performance improvement. A processor may read data resident in a cache faster than it can read data from a system memory, such as system Random Access Memory (RAM), flash or a hard-disk drive (HDD).
In some computer systems, a given processor may be receiving and processing data from a given peripheral. A known process for doing this may be configuring the DMA controller to receive data from the given peripheral and write the data to the system RAM. The given processor may read the data from the system RAM and an associated cache may store the data locally for the processor to process. This process may not provide the most efficient method for providing data to a processor.